Project Settings Project Name IGLOO2_Oversampling_top_syn Implementation Name synthesis Top Module IGLOO2_Oversampling_top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Compile Input Complete 80 230 0 - 0m:03s - 4/18/2014 9:30:51 AM Pre-mapping Complete 59 23 0 0m:01s 0m:01s 143MB 4/18/2014 9:30:54 AM Map & Optimize Complete 48 84 0 0m:04s 0m:05s 165MB 4/18/2014 9:31:00 AM Area Summary Carry Cells 138 Sequential Cells 1010 DSP Blocks (MACC) (dsp_used) 0 I/O Cells 5 Global Clock Buffers 13 LUTs (total_luts) 1099 Timing Summary Clock Name Req Freq Est Freq Slack IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 110.5 MHz 0.947 IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 408.6 MHz 7.553 IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 120.8 MHz 0.862 IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 219.4 MHz 5.443 IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock 100.0 MHz 148.4 MHz 3.262 IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock 100.0 MHz 400.7 MHz 7.504 System 100.0 MHz NA NA Optimizations Summary Combined Clock Conversion 6 / 1